WM8802
Product Preview
READ REGISTER OUTPUT CONTENTS
REGISTER
ADDRESS
DO15
DO14
DO13
DO12
DO11
DO10
DO9
DO8
CCB address; 0xEA
DEMPF
OSLIPO
OPCRNW OUNPCM OCSRNW
OFSCHG
OINDET
OERROR
OERROR
RERR output (Output status during read)
0: No transfer error in PLL locked status
1: Transfer error in PLL unlocked status
OINDET
Data input pin status change (Clear following read)
0: No change in data input pin status
1: Change in data input pin status
OFSCHG
OCSRNW
OUNPCM
OPCRNW
OSLIPO
Input fs calculation update result (clear following read)
0: No input fs calculation update
1: Input fs calculation update
First 48 bit channel status update result (Clear following read)
0: No update
1: Update
output (Output of status during read)
AUDIO
0: Non-PCM signal not detected
1: Non-PCM signal detected
Burst preamble Pc update result (Clear following read)
0: No update
1: Update
Read data twice and detect data loss during slave operation
(Clear following read)
0: No detection
1: Two reads, lost data detected
OEMPF
Channel status emphasis detection (Output status during
read)
0: No pre-emphasis
1: 50/15 µs pre-emphasis
The status of RERR and AUDIO is read according to RESEL and AOSEL settings regardless of the
INT output setting from OERROR and OUNPCM.
PP Rev 1.1 April 2004
56
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
