WM8802
Product Preview
Output data format setting:
REGISTER ADDRESS
CCB address; 0xE8;
Command address: 7
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
0
1
1
1
0
0
CAU
CAL
DI15
DI14
DI13
DI12
DI11
DI10
DI9
DI8
SLRCKP
SBCKP
RLRCKP
RBCKP
0
OFSEL2
OFSEL1
OFSEL0
OFSEL [2:0]
Audio data output format setting
000: I2S data output (initial value)
001: Left Justified data output
010: 24 bit Right Justified data output (master mode only)
011: 20 bit Right Justified data output (master mode only)
100: 16 bit Right Justified data output (master mode only)
101: Reserved
110: Reserved
111: Reserved
RBCKP
RLRCKP
SBCKP
SLRCKP
RBCK output polarity setting
0: Falling RDATA data change (initial value)
1: Rising RDATA data change
RLRCK output polarity setting
0: Low period: L-channel data; High period: R-channel data (initial value)
1: Low period: R-channel data; High period: L-channel data
SBCK output polarity setting
0: Falling RDATA data change (initial value)
1: Falling RDATA data change
SLRCK output polarity setting
0: Low period: L-channel data; High period: R-channel data (initial value)
1: Low period: R-channel data; High period: L-channel data
The data output format and RLRCK output polarity can be set independently. The RLRCH polarity is
set according to each data output format.
PP Rev 1.1 April 2004
48
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
