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WM8802
Digital data input/output port setting:
REGISTER ADDRESS
CCB address: 0xE8;
Command address: 6
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
0
1
1
0
0
0
CAU
CAL
DI15
DI14
DI13
DI12
DI11
DI10
DI9
DI8
RXOFF
ROSEL2
ROSEL1
ROSEL0
ULSEL
RISEL2
RISEL1
RISEL0
RISEL [2:0]
Data demodulation input pin setting
000: RX0 selection (initial value)
001: RX1 selection
010: RX2 selection
011: RX3 selection
100: RX4 selection (However, VI input is performed when VISEL is
set.)
101: RX5 selection (However, UI input is performed when UISEL is
set.)
110: RX6 selection
111: Modulation function output (TXO output data) selection
ULSEL
Input pin setting via PLL unlock
0: Normal setting (initial value)
1: Input data switch setting via PLL unlock
ROSEL [2:0]
RXOUT output data setting
000: RX0 input data (initial value)
001: RX1 input data
010: RX2 input data
011: RX3 input data
100: RX4 input data
101: RX5/VI input data
110: RX6/UI input data
111: Modulation function output (TXO output data) selection
RXOFF
RXOUT output status setting
0: ROSEL0, ROSEL1, ROSEL2 selection data output (initial value)
1: Low fixed output
ULSEL can be set when the oscillation amplifier is set to continuous operation with AMPOPR[0:1]. It
does not operate normally when the oscillation amplifier is stopped.
PP Rev 1.1 April 2004
47
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