Product Preview
WM8777
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
3:1
TXPAIFRX_WL
[2:0]
101
Audio Sample Word Length.
000 = Word Length Not Indicated
TXPAIFRX_WL
MAXPAIFRX_WL=
MAXPAIFRX_WL=
=0
=1
001
010
100
101
110
20 bits
22 bits
23 bits
24 bits
21 bits
16 bits
18 bits
19 bits
20 bits
17 bits
All other combinations reserved
7:4
1:0
ORGSAMP[3:0]
0000
10
Original Sampling Frequency. See S/PDIF specification for
details.
0000 = original sampling frequency not indicated
Secondary Audio Interface format select
00 = right justified mode
0111110
(3Eh)
SAIF_FMT
[1:0]
Secondary
Interface
Control
01 = left justified mode
10 = I²S mode
11 = DSP (early or late) mode
SLRCLK Polarity or DSP Early/Late mode select
2
SAIF_LRP
0
Left Justified / Right Justified/
I2S
DSP Mode
0 = Early DSP mode
1 = Late DSP mode
0 = Standard PDATAIPLRC
Polarity
1 = Inverted PDATAIPLRC
Polarity
3
SAIF_BCP
0
SPBCLK Polarity
0 = Normal SPBCLK.
1 = Inverted SPBCLK.
Input Word Length
00 = 16-bit Mode
01 = 20-bit Mode
10 = 24-bit Mode
5:4
SAIF_WL
[1:0]
10
11 = 32-bit Mode (not supported in right justified mode)
Master Mode MCLK:SLRC ratio select:
000 = 128fs
0111111
(3Fh)
2:0
SAIFRATE[2:0]
010
Secondary
Interface
Master Mode
Control
001 = 192fs
010 = 256fs
011 = 384fs
100 = 512fs
101 = 768fs
110 = 1152fs
3
SMS
0
Maser/Slave interface mode select
0 = Slave Mode – SLRC and SPBCLK are inputs
1 = Master Mode – SLRC and SPBCLK are outputs
Audio interface master clock source when SMS is 1.
00 = MCLK
5:4
SAIFCLKSRC[1:0]
00
01 = GPIO (If ADCCLKSRC is set)
10 = PLL clock
11 = PLL clock
1000000
(40h)
0
SPDINMODE
0
Selects the input circuit type for the S/PDIF input
0 = Normal CMOS input
S/PDIF
Receiver
1 = Comparator input. Compatible with 200mV AC coupled
consumer S/PDIF input signals.
PP Rev 1.94 November 2004
89
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
