Product Preview
WM8777
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0110001
(31h)
5:0
AIN[5:0]
00000
ADC left channel input mux control bits
00000 = UTE
ADC Mux and
Powerdown
Control
00001 = AIN1
00010 = AIN2
00011 = AIN1 + AIN2
……
11111 = AIN1 + AIN2 + AIN3 + AIN4 + AIN5 + AIN6
Input mux and buffer powerdown
0 = Input mux and buffer enabled
1 = Input mux and buffer powered down
VOUT1 Output select (see Figure 28)
VOUT2 Output select (see Figure 28)
Mixer Powerdown select
8
AINPD
1
0110010
(32h)
2:0
5:3
7
MX1[2:0]
MX2[2:0]
OUTPD1
001
001
1
Output Mux
and
Powerdown
Control 1
0 = Powerup
1 = Powerdown
8
OUTPD2
1
Mixer Powerdown select
0 = Powerup
1 = Powerdown
0110011
(33h)
2:0
4:3
7
MX3[2:0]
MX4[1:0]
OUTPD3
001
01
1
VOUT3 Output select (see Figure 28)
VOUT4 Output select (see Figure 29)
Mixer Powerdown select
Output Mux
and
Powerdown
Control 2
0 = Powerup
1 = Powerdown
8
OUTPD4
PLL_K[8:0]
PLL_K[17:9]
1
Mixer Powerdown select
0 = Powerup
1 = Powerdown
0110100
(34h)
8:0
8:0
121 (Hex)
17E (Hex)
Fractional (K) part of PLL input/output frequency ratio (bits 8:0).
PLL Control 1
0110101
(35h)
Fractional (K) part of PLL input/output frequency ratio (bits 17:9).
PLL Control 2
0110110
(36h)
3:0
4
PLL_K[21:18]
CLKOUTSRC
D(Hex)
0
Fractional (K) part of PLL input/output frequency ratio (bits 21:18)
CLKOUT pin source:-
0 = PLL clock output
PLL Control 3
1 = Crystal clock output.
DAC clock source
6
7
8
PLL2DAC
PLL2ADC
PLL2TX
0
0
1
0 = MCLK pin
1 = PLL clock
ADC clock source
0 = MCLK or ADCMLCK pin
1 = PLL clock
S/PDIF TX clock source
0 = MLCK or ADCMCLK pin
1 = PLL clock
0110111
(37h)
0
1
PLLPD
1
0 = Enable PLL
1 = Disable PLL
PLL Control 4
POSTSCALE
FRAC_EN
PRESCALE
PLL_N[4:0]
0
0 = no post scale
1= divide MCLK by 2 after PLL
0 = Integer N only PLL
1 = Integer N and Fractional K PLL
0 = no pre-scale
2
0
0
3
1 = divide MCLK by 2 prior to PLL
8:4
00000
Integer (N) divisor part of PLL input/output frequency ratio. Use
values greater than 5 and less than 13.
PP Rev 1.94 November 2004
87
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
