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WM8777
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
0.001
0.002
0.003
0.004
0.005
0.006
Time(s)
Figure 27 Application and Release of Soft Mute
Figure 27 shows the application and release of MUTE whilst a full amplitude sinusoid is being played
at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to
decay exponentially from the DC level of the last input sample. The output will decay towards VMID
with a time constant of approximately 64 input samples. If MUTE is applied to all channels for 1024
or more input samples the DAC will be muted if IZD is set. When MUTE is de-asserted, the output
will restart immediately from the current input sample.
Note that all other means of muting the DAC channels: setting the PL[3:0] bits to 0, setting the
PDWN bit or setting attenuation to 0 will cause much more abrupt muting of the output.
The Record outputs may be enabled by setting RECEN, where RECEN enables the REC1L and
REC1R outputs.
REGISTER ADDRESS
(16h)
BIT
LABEL
DEFAULT
DESCRIPTION
RECL Output Enable
6:5
RECLEN
00
Mute Control
00 = REC output muted
01 = REC output ADCL
10 = REC output DAC1L
RECR Output Enable
8:7
RECREN
00
00 = REC output muted
01 = REC output ADCR
10 = REC output DAC1R
Table 51 REC Enable Registers
PP Rev 1.94 November 2004
57
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
