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WM8777
ERROR HANDLING
Several kinds of error can be reported when decoding the incoming data. The error bits are written to
a read-only register which can be read back by the user over the serial interface. Reading back this
register will reset it.
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
ADDRESS
(4Bh)
0
UNLOCK
0
PLL Unlock signal.
S/PDIF
Receiver
Error Register
(read-only)
0 = PLL is locked to incoming S/PDIF stream.
1 = PLL is not locked to the incoming S/PDIF stream.
V bit from S/PDIF input stream.
0 = Data word is valid.
1
2
3
4
5
6
7
VALIDITY
PARITYERR
BIP
0
0
0
0
0
0
0
1 = Data word is not valid.
Even Parity check.
0 = No Parity errors detected.
1 = Parity error detected.
Biphase coding of S/PDIF input stream.
0 = Biphase Coding is correct.
1 = Biphase Coding error detected.
Received Channel status bit 1 has changed.
0 = Normal running.
AUDIO_N
PCM_N
1 = Change on AUDIO_N.
PCM_N bit has changed
0 = Normal running.
1 = Change on PCM_N.
CPY_N
Received Channel status bit 2 has changed.
0 = Normal running.
1 = Change on CPY_N.
SPDIF_MODE
S/PDIF mode change.
0: Normal running
1: Change in S/PDIF frequency mode detected.
Table 45 S/PDIF Rx Error Status Register
When an error is detected the INT signal is set high. This is a logical OR of the error bits which can
be output to a GPIO (GPIO1 by default). Error bits can be masked off by setting the mask register. If
an error bit is masked off then that error will not be written to the error register and will not cause a
change on INT.
UNLOCK, VALIDITY, PARITY and BIP generate an interrupt when they go from low to high. These
bits are sticky, i.e. the interrupt will remain until the user reads back the register to clear it. AUDIO_N,
PCM_N, CPY_N and SPDIF_MODE will generate an interrupt on any change in status. The user
can then determine the status of these bits by reading back the S/PDIF status register.
PP Rev 1.94 November 2004
53
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
