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WM8777
The circuit for dealing with UNLOCK, VALIDITY, PARITY and BIP errors is shown in Figure 26.
Error bit[0/1/2/3]
SET
Serial
Interface
Readback
RegisterReadDone
CLR
Set Domiant
Mask bit[0/1/2/3]
INT
Figure 26 S/PDIF Error Handling Circuit for UNLOCK, VALIDITY, PARITY and BIP Errors
NON-AUDIO DETECTION
Non-Audio data is indicated by the AUDIO_N and PCM_N bits. AUDIO_N is recovered from the
Channel Status block. PCM_N is set on detection of the 96-bit IEC-61937 non-audio data sync code,
embedded in the data section of the S/PDIF frame. When either the AUDIO_N or PCM_N bits are set
in the error register, and DAC1 is being used for playback, the DAC will be muted automatically using
the softmute feature. As described above, any change on AUDIO_N or PCM_N will cause an
interrupt to be generated. If the MASK register bit for AUDIO_N or PCM_N is set, then that signal will
not generate an interrupt but will still mute the DAC.
If non-audio data is detected and the DAC has been muted, the user must ensure that audio data is
being input, then clear the error register. The mute on the DAC will be removed when the WM8777
detects that audio data is being received.
GENERAL PURPOSE INPUT AND OUTPUT (GPIO) PINS
The WM8777 has four pins which can be additionally configured as GPIOs, using the registers
shown in Table 48. The GPIO pins can be used to output control and status data decoded by the
S/PDIF receiver
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
(47h)
GPIO
3:0
7:4
GPIO1OP[3:0]
GPIO2OP[3:0]
0000
0001
0000 = INT
0001 = V - Validity
Control 1
(48h)
0010 = U - User Data bit
0011 = C - Channel Status Data
0100 = P - Parity bit
3:0
7:4
GPIO3OP[3:0]
GPOMODEOP
[3:0]
0010
1010
GPIO
0101 = Non-audio (AUDIO_N || PCM_N)
0110 = UNLOCK
Control 2
0111 = CSUD (Channel Status Registers Updated)
1000 = Zero Flag 1 output
1001 = Zero Flag 2 output
1010 = GPIOx set as S/PDIF input (standard CMOS
input buffer). Not valid for GPOMODE.
1011 = GPIOx set as S/PDIF input (‘comparator’ input
for AC coupled consumer S/PDIF signals). Not valid for
GPOMODE.
1100 = Sub Frame clock (1 = sub-frame1, 0 = sub-
frame2)
1101 = Start of Block signal
Table 48 GPIO Control Registers
PP Rev 1.94 November 2004
55
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
