WM8777
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S/PDIF RECEIVER
INPUT SELECTOR
The S/PDIF receiver has one dedicated input, SPIN. There are three other pins which can be
configured as either S/PDIF inputs or general purpose outputs (GPOs). The four S/PDIF inputs go
into a 4:1 mux, allowing one input to go to the S/PDIF receiver for decoding. The S/PDIF receiver can
be powered down using the SPDIFRXD register bit.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
(40h)
0
SPDINMODE
0
Selects the input circuit type for the S/PDIF input
0 = Normal CMOS input
S/PDIF
Receiver
Input Selector
1 = Comparator input. Compatible with 200mV AC
coupled consumer S/PDIF input signals.
5:4
RXINSEL[1:0]
00
S/PDIF Receiver input mux select. Note that the general
purpose inputs must be configured using GPIOxOP to
be either CMOS or comparator inputs if selected by
RXINSEL.
00 = S/PDIF_IN1
01 = S/PDIF_IN2 (GPIO1)
10 = S/PDIF_IN3 (GPIO2)
11 = S/PDIF_IN4 (GPIO3)
Table 39 S/PDIF Rx Input Selection register
AUDIO DATA HANDLING
The S/PDIF receiver recovers the data and VUCP bits from each sub-frame. If the S/PDIF input data
is in PCM format the data can be internally routed to the stereo data input of DAC1. The WM8777
can detect when the data is not in PCM format and will automatically mute the DAC. See Non-Audio
Detection for more detail.
The received data can also be output over the Audio interfaces in any of the data formats supported.
This can be done while simultaneously using DAC1 for playback. The received data may also be re-
transmitted over SPDIFOP.
USER DATA
The WM8777 can output recovered user data received over the GPIO pins. See Table 48 for General
Purpose Pin control.
CHANNEL STATUS DATA
The channel status bits are recovered from the incoming data stream and are used to control various
functions of the device. The recovered MAXPAIFRX_WL and PAIFRX_WL bits are used to truncate
the recovered 24-bit audio word to so that only the appropriate numbers of bits are used by the other
interfaces (except the S/PDIF transmitter which always sees the full 24-bit recovered word).
Should the recovered DEEMPH Channel-bit be set, and DAC1 is used for playback, the de-emphasis
filter is activated for that DAC.
It is assumed that the channel status is stereo and hence only channel 1 data is read. The channel
status data is stored in 5 read-only registers which can be read back over the serial interface (see
Serial Interface Readback). When the channel status data has been recovered and stored in
registers, the CSUD (Channel Status UpDate) bit goes high to indicate that the registers are ready for
readback. It will go low again when the first sub-frame of data from the next block is received. CSUD
can be output to one of the GPIO pins.
PP Rev 1.94 November 2004
50
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
