WM8777
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S/PDIF FORMAT
S/PDIF is a serial, bi-phase-mark encoded data stream. An S/PDIF frame consists of two sub-
frames. Each sub-frame is made up of:
•
Preamble – a synchronization pattern used to identify the start of a 192-frame block or sub-
frame
•
•
•
•
•
•
4-bit Auxiliary Data (AUX) – ordered LSB to MSB
20-bit Audio Data (24-bit when combined with AUX) – ordered LSB to MSB
Validity Bit – a 1 indicates invalid data in that sub-frame
User Bit – over 192-frames, this forms a User Data Block,
Channel Bit – over 192-frames, this forms a Channel Status Block
Parity Bit – used to maintain even parity over the sub-frame(except the preamble)
An S/PDIF Block consists of 192 frames. Channel and User blocks are incorporated within the 192-
frame S/PDIF Block. For Consumer mode (as in the WM8777) only the first 40-frames are used to
make up the Channel and User blocks. Figure 25 illustrates the S/PDIF format.
Frame
192
Frame
1
. . . . . . . . .
Subframe 1
Subframe 2
0
3 4
7 8
27 28
31
32 bit
Word
Sync
preamble
Aux
Audio Sample Word
V
U
C
P
Figure 25 S/PDIF Format
CLOCK RECOVERY AND GENERATION
The circuit comprises data and clock recovery blocks, and a clock synthesis function in the event of
no S/PDIF input. As an integral part of these functions, an accurate, stable, crystal derived master
clock must be input to the WM8777. This clock may be generated using the WM8777 crystal
oscillator circuit, by connecting a suitable crystal across the XIN XOP pins, or else may be applied as
a digital input to the XIN pin. This reference clock input may have any frequency from 10MHz up to
27MHz. When S/PDIF signals are being received, the PLL will recover the audio MCLK at a rate of
256fs or 384fs. In the event of no S/PDIF input, the PLL will continue to synthesise a 128, 256 or
384fs audio clock. If desired the S/PDIF input may be ignored and the PLL instructed to synthesise
any desired audio clock rate (depending upon sample rate). The ratio of this audio clock to the
reference clock frequency is set by programming the required value over the serial interface. Audio
sample rates from 32kHz to 96kHz are supported both by the S/PDIF transceiver and the clock
synthesiser.
The reference clock input should be low jitter, hence it is recommended that a crystal connected to
WM8777 oscillator is used to generate the clock. In this condition very low jitter audio clocks will be
generated, and S/PDIF in-coming clocks will likewise be de-jittered. The WM8777 crystal derived
clock, or the PLL derived audio clock, may then be supplied to external circuits as low jitter clock
references as required.
PP Rev 1.94 November 2004
46
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
