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WM8777SEFT 参数 Datasheet PDF下载

WM8777SEFT图片预览
型号: WM8777SEFT
PDF下载: 下载PDF文件 查看货源
内容描述: 24位192KHZ AV接收机芯片 [24 BIT 192KHZ AV RECEIVER ON A CHIP]
分类和应用: 接收机
文件页数/大小: 102 页 / 1257 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Product Preview  
WM8777  
S/PDIF TRANSMITTER  
The S/PDIF transmitter generates the S/PDIF frames, and outputs on the SPDIFOP pin. The audio  
data for the frame can be taken from one of four sources, selectable using the TXSRC register. The  
transmitter can be powered down using the SPDIFTXD register bit.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
(41h)  
2:1  
TXSRC[1:0]  
00  
S/PDIF Transmitter Data Source.  
00 = S/PDIF received data.  
Interface Source  
Select  
01 = ADC digital output data.  
10 = Secondary Audio Interface received data  
11 = Primary Audio Interface Received data.  
3
6
TXRXTHRU  
SPDIFTXD  
0
1
Only used if TXSRC==00. Configures only the Channel  
Bit in the S/PDIF frame.  
0 = Channel data equal to recovered channel data.  
1 = Channel data taken from channel status registers.  
SPDIF_TX powerdown  
(1Ah)  
Powerdown  
Control  
0 = SPDIF_TX enabled  
1 = SPDIF_TX disabled  
Table 33 S/PDIF Tx Control  
The WM8777 also transmits the preamble and VUCP bits (Validity, User Data, Channel Status and  
Parity bits).  
VALIDITY BIT  
Set to 0 (to indicate valid data) – unless TXSRC=00 (S/PDIF receiver), where Validity is set by the  
receiver.  
USER DATA  
Set to 0 as User Data configuration is not supported in the WM8777 – if TXSRC=00 (S/PDIF  
receiver) User Data is set by the receiver.  
CHANNEL STATUS  
The Channel Status bits form a 192-frame block - transmitted at 1 bit per sub-frame. Each sub-frame  
forms its own 192-frame block. The WM8777 is a consumer mode device and only the first 40 bits of  
the block are used. All data transmitted from the WM8777 is stereo, so the channel status data is  
duplicated for both channels. The only exception to this is the channel number bits (23:20) which can  
be changed to indicate if the channel is left or right in the stereo image. Bits within this block can be  
configured by setting the Channel Bit Control registers (see Tables 28-32 ). If TXSRC is the S/PDIF  
receiver, the Channel bits are transmitted with the same values recovered by the receiver – unless  
TXRXTHRU is set, in which case they are set by the registers.  
Note that the WM8777 expects to receive channel status data in consumer format. The channel  
status bits are defined differently for professional mode. The definitions on the following page do not  
hold for professional mode.  
PARITY BIT  
This bit maintains even parity for data as a means of basic error detection. It is generated by the  
transmitter.  
PP Rev 1.94 November 2004  
47  
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