WM8777
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
(18h)
6
MCLKOPEN
0
MCLK pin output enable
0 = MCLK pin is an input
Primary
Interface Control
(RX)
1 = MCLK pin is an output (refer to
MCLKOUTSRC below
7
MCLKOUTSRC
0
MCLK pin output source
0 = PLL
1 = Crystal clock output.
(34h)
8:0
8:0
PLL_K[8:0]
121 (Hex)
17E (Hex)
Fractional (K) part of PLL
input/output frequency ratio (treat as
one 22-digit binary number).
PLL Control 1
(35h)
PLL_K[17:9]
PLL Control 2
(36h)
3:0
4
PLL_K[21:18]
CLKOUTSRC
D(Hex)
0
PLL Control 3
CLKOUT pin source:-
0 = PLL clock output
1 = Crystal clock output.
DAC clock source
6
7
8
PLL2DAC
PLL2ADC
PLL2TX
0
0
1
0 = MCLK pin
1 = PLL clock
ADC clock source
0 = MCLK or ADCMLCK pin
1 = PLL clock
S/PDIF TX clock source
0 = MLCK or ADCMCLK pin
1 = PLL clock
(37h)
0
PLLPD
1
0 = Enable PLL
PLL Control 4
1 = Disable PLL
1
POSTSCALE
FRAC_EN
PRESCALE
PLL_N[4:0]
0
0 = no post scale
1= divide PLL by 2 after PLL
0 = Integer N only PLL
1 = Integer N and Fractional K PLL
0 = no pre-scale
2
0
3
0
1 = divide MCLK by 2 prior to PLL
8:4
00000
Integer (N) divisor part of PLL
input/output frequency ratio. Use
values greater than 5 and less than
13.
(40h)
8
ADCCLKSRC
0
ADC clock source
S/PDIF
0 = ADCMCLK is from MCLK pin
and ADCPBCLK is from PBCLK pin.
Receiver
Input Selector
1 = ADCMCLK is from GPIO1, and
ADCPBCLK is from GPIO2.(Note
that when in this mode RXINSEL
must not be set to 01 or 10)
Table 31 PLL Frequency Ratio Control
Note: MCLKOPEN should not be toggled if any part of the WM8777 is actively using
MCLK as its clock source.
PP Rev 1.94 November 2004
44
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
