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WM8777SEFT 参数 Datasheet PDF下载

WM8777SEFT图片预览
型号: WM8777SEFT
PDF下载: 下载PDF文件 查看货源
内容描述: 24位192KHZ AV接收机芯片 [24 BIT 192KHZ AV RECEIVER ON A CHIP]
分类和应用: 接收机
文件页数/大小: 102 页 / 1257 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
 浏览型号WM8777SEFT的Datasheet PDF文件第41页浏览型号WM8777SEFT的Datasheet PDF文件第42页浏览型号WM8777SEFT的Datasheet PDF文件第43页浏览型号WM8777SEFT的Datasheet PDF文件第44页浏览型号WM8777SEFT的Datasheet PDF文件第46页浏览型号WM8777SEFT的Datasheet PDF文件第47页浏览型号WM8777SEFT的Datasheet PDF文件第48页浏览型号WM8777SEFT的Datasheet PDF文件第49页  
Product Preview  
WM8777  
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings are shown below.  
XTALC  
LK  
DESIRED  
OUTPUT  
(MHz)  
F2  
PRE  
POST  
SCALE  
R
N
K
(MHz)  
SCALE  
(Hex)  
(Hex)  
(MHz)  
(F1)  
11.91  
11.91  
12  
11.2896  
12.288  
11.2896  
12.288  
11.2896  
12.288  
11.2896  
12.288  
11.2896  
12.288  
11.2896  
12.288  
11.2896  
12.288  
11.2896  
12.288  
11.2896  
12.288  
11.2896  
12.288  
90.3168  
98.304  
90.3168  
98.304  
90.3168  
98.304  
90.3168  
98.304  
90.3168  
98.304  
90.3168  
98.304  
90.3168  
98.304  
90.3168  
98.304  
90.3168  
98.304  
90.3168  
98.304  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7.5833  
8.2539  
7.5264  
8.192  
7
8
7
8
6
7
6
6
9
A
9
9
9
9
7
8
6
7
6
7
25545C  
103FF6  
21B089  
C49BA  
3CA2F4  
23F548  
116872  
34E818  
1A1CAC  
F5C28  
12  
13  
6.9474  
7.5618  
6.272  
13  
14.4  
14.4  
19.2  
19.2  
19.68  
19.68  
19.8  
19.8  
24  
6.8267  
9.408  
10.24  
9.1785  
9.9902  
9.1229  
9.9297  
7.5264  
8.192  
B6D22  
3F6017  
7DDCA  
3B8023  
21B089  
C49BA  
3CA2F4  
23F548  
2C2B30  
12089E  
24  
26  
6.9474  
7.5618  
6.6901  
7.2818  
26  
27  
27  
Table 32 PLL Frequency Examples  
S/PDIF TRANSCEIVER FEATURES  
IEC-60958 compatible with 32 to 96k frames/s support  
Support for Rx and Tx of S/PDIF data  
Clock synthesis PLL with reference clock input and low jitter output  
Input mux with support for up to 4 S/PDIF inputs  
Register controlled Channel Status bit configuration  
Register read-back of recovered Channel Status bits and error flags  
Detection of non-audio data, sample rate, de-emphasis  
Programmable GPO for error flags and frame status flags  
An IEC-60958 compatible S/PDIF transceiver is integrated into the WM8777. Operation of the  
S/PDIF function may be synchronous or asynchronous to the rest of the digital audio circuits.  
The receiver performs data and clock recovery, and sends recovered data either off the chip to an  
external DSP (via Primary or Secondary Audio Interfaces), or if the data is audio PCM, it can route  
the stereo recovered data to DAC1. The recovered clock may be routed out of the chip onto a pin for  
external use, and may be used to clock the internal DAC and ADC circuits as required.  
The transmitter generates S/PDIF frames where audio data may be sourced from the ADC, S/PDIF  
Receiver, Primary or Secondary Audio Interfaces.  
PP Rev 1.94 November 2004  
45  
w
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