WM8777
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MASTER CLOCK AND PHASE LOCKED LOOP
The WM8777 has an on-chip phase-locked loop (PLL) circuit that can be used to:
•
•
Generate master clocks for the WM8777 audio functions from another external clock.
Generate a clock for another part of the system from an existing audio master clock.
Figure 23 PLL and Clock Select Circuit
The PLL frequency ratio R = f2/f1 (see Figure 23 ) can be set using K and N (see :
N = int R
K = int (222 (R-N))
Example:
MCLK=12MHz, required clock = 12.288MHz.
R should be chosen to ensure 5 < N < 13. There is a divide by 4 and a selectable divide by 2
after the PLL which should be set to meet this requirement. Enabling the divide by 2 sets the
required f2 = 8 x 12.288MHz = 98.304MHz.
R = 98.304 / 12 = 8.192
N = int R = 8
k = int ( 222 x (8.192 – 8)) = 805306 = C49BAh
PP Rev 1.94 November 2004
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
