WM8777
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DIGITAL AUDIO INTERFACE CONTROL REGISTERS
Interface format for primary and secondary interfaces are selected via the PAIFRX_FMT register bits:
REGISTER ADDRESS
(18h)
BIT
LABEL
DEFAULT
DESCRIPTION
Interface Format Select
00 = right justified mode
01 = left justified mode
10 = I2S mode
1:0 PAIFRX_FMT
[1:0]
10
Primary
Interface Control (RX)
11 = DSP (early or late)
mode
(1Bh)
1:0
1:0
PAIFTX_FMT
[1:0]
10
10
Primary Interface
Control (TX)
(3Eh)
SAIF_FMT
[1:0]
Secondary Interface
Control
Table 25 Format Registers
In left justified, right justified or I2S modes, the PAIFRX_LRP register bit controls the polarity of
PDATAIPLRC/PDATAOPLRC/SLRC. If this bit is set high, the expected polarity of
PDATAIPLRC/PDATAOPLRC/SLRC will be the opposite of that shown in Figure 16, Figure 17 and
Figure 18.
Note that if this feature is used as a means of swapping the left and right channels, a 1 sample
phase difference will be introduced. In DSP modes, the PAIFRX_LRP register bit is used to select
between early and late modes.
REGISTER ADDRESS
(18h)
BIT
LABEL
DEFAULT
DESCRIPTION
In LEFT/RIGHT/I2S modes:
2
PAIFRX_LRP
0
Primary
PDATAOPLRC/PDATAIPLRC/SLRC
Polarity (normal)
Interface Control (RX)
0 = normal LRCLK polarity
1 = inverted LRCLK polarity
(1Bh)
2
2
PAIFTX_LRP
SAIF_LRP
0
0
In DSP mode:
Primary Interface
Control (TX)
0 = Early DSP mode
1 = Late DSP mode
(3Eh)
Secondary Interface
Control
Table 26 LRCLK Polarity Registers
By default, PDATAIPLRC, PDATAOPLRC, SLRC, PDATAIP1/2/3/4 and SDATAIP are sampled on
the rising edge of PBCLK/SPBCLK and should ideally change on the falling edge. Data sources that
change PDATAIPLRC, PDATAOPLRC, SLRC, PDATAIP1/2/3/4 and SDATAOP on the rising edge of
PBCLK/SPBCLK can be supported by setting the PAIFRX_BCP register bit. Setting PAIFRX_BCP to
1 inverts the polarity of PBCLK/SPBCLK to the inverse of that shown in Figure 19, Figure 20, Figure
21 and Figure 22.
REGISTER ADDRESS
(18h)
BIT
LABEL
DEFAULT
DESCRIPTION
3
PAIFRX_BCP
0
PBCLK/SPBCLK Polarity (DSP
modes)
Primary
0 = normal PBCLK polarity
1 = inverted PBCLK polarity
Interface Control (RX)
(1Bh)
3
3
PAIFTX_BCP
SAIF_BCP
0
0
Primary Interface
Control (TX)
(3Eh)
Secondary Interface
Control
Table 27 PBCLK Polarity Registers
The PAIFRX_WL[1:0] bits are used to control the input word length.
Note: If 32-bit mode is selected in right justified mode, the WM8777 defaults to 24 bits.
PP Rev 1.94 November 2004
38
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
