WM8773
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POWERDOWN MODE AND ADC DISABLE
Setting the PDWN register bit immediately powers down the WM8773, including the references,
overriding all other powerdown control bits. All trace of the previous input samples are removed, but
all control register settings are preserved. When PDWN is cleared the digital filters will be
reinitialised. It is recommended that the 8-channel input mux and buffer, and ADC are powered down
before setting PDWN.
REGISTER ADDRESS
11000
BIT
LABEL
DEFAULT
DESCRIPTION
Power Down Mode Select:
0 : Normal Mode
0
PDWN
0
Powerdown Control
1: Power Down Mode
The ADC may also be powered down by setting the ADCD disable bit. Setting ADCD will disable the
ADC and select a low power mode. The ADC digital filters will be reset and will reinitialise when
ADCD is reset.
REGISTER ADDRESS
11000
BIT
LABEL
DEFAULT
DESCRIPTION
ADC Disable:
1
ADCD
1
ADC Powerdown Control
0 : Normal Mode
1: Power Down Mode
ADC GAIN CONTROL
Control bits LAG[4:0] and RAG[4:0] control the ADC input gain, allowing the user to attenuate the
ADC input signal to match the full-scale range of the ADC. The gain is independently adjustable on
left and right inputs. Left and right inputs may also be independently muted. The LRBOTH control bit
allows the user to write the same attenuation value to both left and right volume control registers. The
ADC volume and mute also applies to the bypass signal path.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
11001
Attenuation
ADCL
4:0
LAG[4:0]
01100
(0dB)
0
Attenuation data for Left channel ADC gain in 1dB steps. See Table
8
5
MUTE
Mute for Left channel ADC:
0: Mute off
1: Mute on
6
LRBOTH
RAG[4:0]
0
Setting LRBOTH will write the same gain value to LAG[4:0] and
RAG[4:0]
11010
4:0
01100
(0dB)
0
Attenuation data for right channel ADC gain in 1dB steps. See Table
8
Attenuation
ADCR
5
6
MUTE
Mute for Right channel ADC:
0: Mute off
1: Mute on
LRBOTH
0
Setting LRBOTH will write the same gain value to RAG[4:0] and
LAG[4:0]
PP Rev 1.0 June 2002
20
ꢀꢀ
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
