WM8770
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
00110
6:0
L4A[6:0]
1111111
(0dB)
0
Attenuation Data for Left Channel DACL4 in 1dB steps. See Table
11
Analogue
Attenuation
DACL4
7
8
L4ZCEN
UPDATE
DACL2 Zero Cross Detect Enable
0: zero cross disabled
1: zero cross enabled
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store DACL4 in intermediate latch (no change to output)
1: Store DACL4 and update attenuation on all channels.
00111
6:0
7
R4A[6:0]
R4ZCEN
1111111
(0dB)
0
Attenuation Data for Left Channel DACL4 in 1dB steps. See Table
11
Analogue
Attenuation
DACR4
DACR2 Zero Cross Detect Enable
0: zero cross disabled
1: zero cross enabled
8
UPDATE
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store DACR4 in intermediate latch (no change to output)
1: Store DACR4 and update attenuation on all channels.
Attenuation Data for all DAC Gains in 1dB steps. See Table 11
01000
6:0
7
MASTA[6:0]
MZCEN
1111111
(0dB)
0
Analogue
Master
Master Zero Cross Detect Enable
Attenuation
0: zero cross disabled
(all channels)
1: zero cross enabled
8
UPDATE
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store gains in intermediate latch (no change to output)
1: Store gains and update attenuation on all channels.
01001
7:0
8
LDA1[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation Data for Left Channel DACL1 in 0.5dB steps.
See Table 12
Digital
Attenuation
DACL1
Not latched
Controls simultaneous Update of all Attenuation Latches
0: Store LDA1 in intermediate latch (no change to output)
1: Store LDA1 and update attenuation on all channels
01010
7:0
8
RDA1[6:0]
UPDATE
11111111
(0dB)
Digital Attenuation Data for Right Channel DACR1 in 0.5dB steps.
See Table 12
Digital
Attenuation
DACR1
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store RDA1 in intermediate latch (no change to output)
1: Store RDA1 and update attenuation on all channels.
01011
7:0
8
LDA2[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation data for Left channel DACL2 in 0.5dB steps.
See Table 12
Digital
Attenuation
DACL2
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store LDA2 in intermediate latch (no change to output)
1: Store LDA2 and update attenuation on all channels.
01100
7:0
8
RDA2[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation Data for Right Channel DACR2 in 0.5dB steps.
See Table 12
Digital
Attenuation
DACR2
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store RDA2 in intermediate latch (no change to output)
1: Store RDA2 and update attenuation on all channels.
01101
7:0
8
LDA3[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation Data for Left Channel DACL3 in 0.5dB steps.
See Table 12
Digital
Attenuation
DACL3
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store LDA3 in intermediate latch (no change to output)
1: Store LDA3 and update attenuation on all channels.
PD Rev 4.1 June 2005
40
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
