WM8770
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
DAC Channel Soft Mute Enables:
10100
3:0
DMUTE[3:0]
0000
Mute Control
0: mute disabled
1: mute enabled
4
MUTEALL
RECEN
0
DAC Channel Master Soft Mute. Mutes all DAC channels:
0: mute disabled
1: mute enabled
5
0
REC Output Enable
0 : REC output muted
1: REC output enabled
10101
3:0
7:4
DEEMP[3:0]
DZFM[3:0]
0000
0000
De-emphasis Mode Select:
0 : Normal Mode
DAC Control
1: De-emphasis Mode
Selects the ouput for ZFLG1 and ZFLG2 pins (see Table 9).
1: indicates 1024 consecutive zero input samples on the
channels selected
0: indicates at least one of selected channels has non
zero sample in last 1024 inputs
1:0
FMT[1:0]
10
Interface Format Select
10110
00: right justified mode
Interface
Control
01: left justified mode
10: I2S mode
11: DSP mode
2
3
LRP
BCP
0
0
ADCLRC/DACLRC Polarity or DSP Early/Late mode select
Left Justified / Right Justified /
I2S
DSP Mode
0: Early DSP mode
1: Late DSP mode
0: Standard DACLRC Polarity
1: Inverted DACLRC Polarity
BITCLK Polarity
0: Normal - DIN[3:0], DACLRC & ADCLRC sampled on
rising edge of BCLK; DOUT changes on falling edge of
BCLK.
1: Inverted - DIN[3:0], DACLRC & ADCLRC sampled on
falling edge of BCLK; DOUT changes on rising edge of
BCLK.
5:4
WL[1:0]
10
0
Input Word Length
00: 16-bit Mode
01: 20-bit Mode
10: 24-bit Mode
11: 32-bit Mode (not supported in right justified mode)
ADC Highpass Filter Disable:
0: Highpass Filter enabled
1: Highpass Filter disabled
8
ADCHPD
PD Rev 4.1 June 2005
42
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
