Production Data
WM8770
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
10111
2:0
ADCRATE[2:0]
010
Master Mode MCLK:ADCLRC Ratio Select:
010: 256fs
Master Mode
Control
011: 384fs
100: 512fs
3
ADCOSR
0
ADC oversample rate select
0: 128x oversampling
1: 64x oversapmling
Master Mode MCLK:DACLRC Ratio Select:
000: 128fs
6:4
DACRATE[2:0]
010
001: 192fs
010: 256fs
011: 384fs
100: 512fs
8
0
MS
0
0
Maser/Slave Interface Mode Select
0: Slave Mode – ADCLRC, DACLRC and BCLK are inputs
1: Master Mode – ADCLRC, DACLRC and BCLK are outputs
11000
PWDN
Chip Powerdown Control (works in tandem with ADCD and
DACD):
Powerdown
Control
0: All circuits running, outputs are active
1: All circuits in power save mode, outputs muted
ADC Powerdown:
1
ADCD
1
0: ADC enabled
1: ADC disabled
5:2
DACD[3:0]
1111
DAC Powerdown
0: DAC enabled
1: DAC disabled
11001
4:0
5
LAG[4:0]
MUTE
01100
(0dB)
0
Attenuation Data for Left Channel ADC Gain in 1dB steps
Attenuation
ADCL
Mute for Left Channel ADC:
0: Mute off
1: Mute on
6
7
LRBOTH
0
0
Setting LRBOTH will write the same gain value to LAG[4:0] and
RAG[4:0]
ADCMUTE
Mute for Left and Right Channel ADC:
0: Mute off
1: Mute on
11010
4:0
5
RAG[4:0]
MUTE
01100
(0dB)
0
Attenuation Data for Right Channel ADC gain in 1dB steps
Attenuation
ADCR
Mute for Right Channel ADC:
0: Mute off
1: Mute on
6
LRBOTH
0
Setting LRBOTH will write the same gain value to RAG[4:0] and
LAG[4:0]
11011
2:0
6:4
8
LMX[2:0]
RMX[2:0]
AINPD
000
000
1
ADC left channel input mux control bits
ADC right channel input mux control bits
Input mux and buffer powerdown
ADC Mux and
Powerdown
Control
0: Input mux and buffer enabled
1: Input mux and buffer powered down
PD Rev 4.1 June 2005
43
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
