Production Data
WM8770
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
01110
7:0
RDA3[7:0]
11111111
(0dB)
Digital Attenuation Data for Right channel DACR3 in 0.5dB steps.
See Table 12
Digital
Attenuation
DACR3
8
UPDATE
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store RDA3 in intermediate latch (no change to output)
1: Store RDA3 and update attenuation on all channels.
01111
7:0
8
LDA4[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation Data for Left Channel DACL4 in 0.5dB steps.
See Table 12
Digital
Attenuation
DACL4
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store LDA4 in intermediate latch (no change to output)
1: Store LDA4 and update attenuation on all channels.
10000
7:0
8
RDA4[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation Data for Right Channel DACR4 in 0.5dB steps.
See Table 12
Digital
Attenuation
DACR4
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store RDA4 in intermediate latch (no change to output)
1: Store RDA4 and update attenuation on all channels.
10001
7:0
8
MASTDA[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation Data for all DAC Channels in 0.5dB steps. See
Table 12
Master
Digital
Attenuation
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store gain in intermediate latch (no change to output)
1: Store gain and update attenuation on all channels.
Controls Phase of DAC Outputs
(all channels)
10010
7:0
0
PHASE
DZCEN
ATC
00000000
Phase swaps
0: Sets non inverted output phase
1: inverts phase of DAC output
10011
0
0
DAC Digital Volume Zero Cross Enable:
0: Zero Cross detect disabled
DAC Control
1: Zero Cross detect enabled
Attenuator Control
1
0: All DACs use attenuations as programmed.
1: Right channel DACs use corresponding left DAC
attenuations
2
IZD
0
Infinite Zero Detection Circuit Control and Automute Control
0: Infinite zero detect automute disabled
1: Infinite zero detect automute enabled
DAC Analogue Zero Cross Detect Timeout Disable
0 : Timeout enabled
3
TOD
0
1: Timeout disabled
7:4
PL[3:0]
1001
DAC Output Control
PL[3:0]
Left
Right
PL[3:0]
Left
Right
Output
Output
Output
Output
0000
0001
0010
0011
0100
0101
0110
0111
Mute
Left
Mute
Mute
Mute
Mute
Left
1000
1001
1010
1011
1100
1101
1110
1111
Mute
Left
Right
Right
Right
(L+R)/2
Mute
Left
Right
(L+R)/2
Mute
Left
Right
Right
(L+R)/2
(L+R)/2
(L+R)/2
(L+R)/2
Left
Right
(L+R)/2
Left
Right
(L+R)/2
Left
PD Rev 4.1 June 2005
41
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
