WM8770
Production Data
DSP LATE MODE
In DSP late mode, the MSB of DAC channel 1 left data is sampled by the WM8770 on the first BCLK
rising edge following a DACLRC rising edge. DAC channel 1 right and DAC channels 2, 3 and 4 data
follow DAC channel 1 left data (Figure 19).
1/fs
DACLRC
BCK
CHANNEL 1
LEFT
CHANNEL 1
RIGHT
CHANNEL 2
LEFT
CHANNEL 4
RIGHT
NO VALID DATA
DIN1
1
2
n
1
2
n
1
2
n
1
n-1
n-1
n-1
MSB
LSB
Input Word Length (IWL)
Figure 19 DSP Late Mode Timing Diagram – DAC Data Input
The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of
BCLK as the low to high ADCLRC transition and may be sampled on the rising edge of BCLK. The
right channel ADC data is contiguous with the left channel data (Figure 20).
1/fs
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
1
2
n
1
2
n
1
n-1
n-1
DOUT
MSB
LSB
Input Word Length (IWL)
Figure 20 DSP Late Mode Timing Diagram – ADC Data Output
In both early and late DSP modes, DACL1 is always sent first, followed immediately by DACR1 and
the data words for the other 6 channels. No BCLK edges are allowed between the data words. The
word order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right, DAC4 left, DAC4
right.
CONTROL INTERFACE OPERATION
The WM8770 is controlled using a 3-wire serial interface in either an SPI compatible
configuration or a CCB (Computer Control Bus) configuration.
The interface configuration is determined by the state of the CE pin on the rising edge of the
RESETB pin. If the CE pin is low on the rising edge of RESETB, CCB configuration is selected. If CE
is high on the rising edge of RESETB, SPI compatible configuration is selected.
The control interface is 5V tolerant, meaning that the control interface input signals CE, CL and DI
may have an input high level of 5V while DVDD is 3V. Input thresholds are determined by DVDD.
RESETB is also 5V tolerant.
PD Rev 4.1 June 2005
24
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
