WM8746
Production Data
RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN
transition. LRCIN is high during the left samples and low during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN0/1/2
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 5 Right Justified Mode Timing Diagram
I2S MODE
In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN transition.
LRCIN is low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
1 BCKIN
1 BCKIN
DIN0/1/2
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 6 I2S Mode Timing Diagram
DSP MODE A
In DSP mode A, the first bit is sampled on the BCKIN edge following the one which detects a low to
high transition on LRCIN.
1 BCKIN
1 BCKIN
1/fs
LRCIN
BCKIN
CHANNEL 0
LEFT
CHANNEL 0
RIGHT
CHANNEL 1
LEFT
CHANNEL 2
RIGHT
NO VALID DATA
1
2
n
1
2
n
1
2
n
DIN0
n-1
n-1
n-1
MSB
LSB
Input Word Length (IWL)
Figure 7 DSP Mode A Timing Diagram
March 2006, PD Rev 4.0
12
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
