WM8746
Production Data
MASTER CLOCK TIMING
tSCKIL
SCKI
tSCKIH
tSCKIY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
SCKI System clock pulse width high
SCKI System clock pulse width low
SCKI System clock cycle time
SCKI Duty cycle
tSCKIH
tSCKIL
tSCKIY
13
13
ns
ns
ns
26
40:60
60:40
Table 1 Master Clock Timing Requirements
DIGITAL AUDIO INTERFACE TIMING
tBCH
tBCL
BCLK
tBCY
DACLRC
DIN0/1/2
tLRSU
tDS
tLRH
tDH
Figure 2 PCM Digital Audio Data Timing
Test Conditions
AVDD = DVDD = 5V, AGND = GR = DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCKIN cycle time
tBCY
tBCH
tBCL
tLB
40
16
16
8
ns
ns
ns
ns
BCKIN pulse width high
BCKIN pulse width low
LRCIN set-up time to
BCKIN rising edge
LRCIN hold time from
BCKIN rising edge
tBL
tDS
tDH
8
8
8
ns
ns
ns
DIN0/1/2 set-up time to
BCKIN rising edge
DIN0/1/2 hold time from
BCKIN rising edge
Table 2 PCM Digital Audio Timing
March 2006, PD Rev 4.0
8
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
