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WM8746SEDS 参数 Datasheet PDF下载

WM8746SEDS图片预览
型号: WM8746SEDS
PDF下载: 下载PDF文件 查看货源
内容描述: 24位, 192kHz的6通道DAC,具有音量控制 [24-bit, 192kHz 6-Channel DAC with Volume Control]
分类和应用:
文件页数/大小: 32 页 / 387 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8746  
Production Data  
DEVICE DESCRIPTION  
INTRODUCTION  
WM8746 is a complete 6-channel stereo audio digital-to-analogue converter, including digital  
interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC and  
output smoothing filters.  
The device is implemented as three separate stereo DACs in a single package and controlled by a  
single interface. Each DAC has its own data input DIN0/1/2, and LRCIN, BCKIN and SCKI are  
shared between them. An additional LRCIN2 input is provided to allow for the front channels in a  
surround system to be run at higher sample rate than the other 4 channels (ie. 192kHz for front  
channels and 96kHz). In this mode the same SCKI is used for all channels, the front channels being  
run at twice the over-sampling rate of the other channels.  
Control of internal functionality of the device is by either hardware control (pin programmed) or  
software control (3-wire serial control interface). The MODE pin selects between hardware and  
software control. In software control mode, an SPI type interface is used. This interface may be  
asynchronous to the audio data interface. Control data will be re-synchronised to the audio  
processing internally.  
Operation using a system clock of 256fs, 384fs, 512fs or 768fs is provided, selection between clock  
rates being automatically detected. Sample rates (fs) from less than 8kHz to 96kHz are allowed,  
provided the appropriate system clock is input. Support is also provided for up to 192kHz using a  
system clock of 128fs or 192fs.  
The audio data interface supports right, left and I2S interface formats along with a highly flexible DSP  
serial port interface. When in hardware mode, the three serial interface pins become control pins to  
allow selection of input data format type (I2S or right justified), input word length (16, 20, 24, or 32-bit)  
and de-emphasis functions.  
AUDIO DATA SAMPLING RATES  
In a typical digital audio system there is only one central clock source producing a reference clock to  
which all audio data processing is synchronised. This clock is often referred to as the audio system’s  
Master Clock. The external master system clock can be applied directly through the SCKI input pin  
with no software configuration necessary. Note that on the WM8746, SCKI is used to derive clocks  
for the DAC path. The DAC path consists of DAC sampling clock, DAC digital filter clock and DAC  
digital audio interface timing. In a system where there are a number of possible sources for the  
reference clock it is recommended that the clock source with the lowest jitter be used to optimise the  
performance of the DAC.  
The system clock for WM8746 supports audio sampling rates from 128fs to 768fs, where fs is the  
audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The system  
clock is used to operate the digital filters and the noise shaping circuits.  
The WM8746 has a system clock detection circuit that automatically determines the relationship  
between the system clock frequency and the sampling rate (to within +/- 32 system clocks). If greater  
than 32 clocks error, the interface defaults to 768fs and maintains the output level at the last sample.  
The system clock should be synchronised with LRCIN, although the WM8746 is tolerant of phase  
differences or jitter on this clock. Table 4 shows the typical system clock frequency inputs for the  
WM8746.  
SAMPLING  
RATE (FS)  
SYSTEM CLOCK FREQUENCY (MHZ)  
128fs  
192fs  
256fs  
384fs  
512fs  
768fs  
(LRCIN)  
32kHz  
4.096  
5.6448  
6.144  
6.144  
8.467  
8.192  
11.2896  
12.288  
24.576  
12.288  
16.9340  
18.432  
36.864  
16.384  
22.5792  
24.576  
24.576  
33.8688  
36.864  
44.1kHz  
48kHz  
9.216  
96kHz  
12.288  
24.576  
18.432  
36.864  
Unavailable Unavailable  
192kHz  
Unavailable Unavailable Unavailable Unavailable  
Table 4 System Clock Frequencies Versus Sampling Rate  
March 2006, PD Rev 4.0  
10  
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