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WM8746SEDS 参数 Datasheet PDF下载

WM8746SEDS图片预览
型号: WM8746SEDS
PDF下载: 下载PDF文件 查看货源
内容描述: 24位, 192kHz的6通道DAC,具有音量控制 [24-bit, 192kHz 6-Channel DAC with Volume Control]
分类和应用:
文件页数/大小: 32 页 / 387 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8746  
Production Data  
DSP MODE B  
In DSP mode B, the first bit is sampled on the BCKIN edge which detects a low to high transition on  
LRCIN.  
1/fs  
LRCIN  
BCKIN  
CHANNEL 0  
LEFT  
CHANNEL 0  
RIGHT  
CHANNEL 1  
LEFT  
CHANNEL 2  
RIGHT  
NO VALID DATA  
1
2
n
1
2
n
1
2
n
1
DIN0  
n-1  
n-1  
n-1  
MSB  
LSB  
Input Word Length (IWL)  
Figure 8 DSP Mode B Timing Diagram  
In both DSP modes, DAC0 left is always sent first, followed immediately by data words for the other 5  
channels. No BCKIN edges are allowed between the data words. The word order is DAC0 left, DAC0  
right, DAC1 left, DAC1 right, DAC2 left, DAC2 right.  
SPLIT RATE MODE  
The WM8746 can be used with differing sample rates on the front and rear channels. This allows  
extremely high quality audio to be played on the front two channels whilst the other channels use  
normal high quality data streams.  
This mode will only work with a front data rate of 192kHz and a rear rate of 96kHz but can be used  
with all the normal data formats except the two DSP modes and with the system at either 128fs or  
192fs see Table 4.  
When running in split rate mode all the channels are clocked in using a common BCKIN; the front  
channels using LRCIN and all the other channels using LRCIN2 see Figure 9.  
2/fs  
LEFT CHANNEL  
LEFT CHANNEL  
RIGHT CHANNEL  
RIGHT CHANNEL  
LRCIN  
BCKIN  
DIN0  
1
2
n
1
2
n
1
2
n
1
2
n
LSB MSB  
MSB  
LSB MSB  
MSB  
LSB  
LSB  
LRCIN2  
DIN1/2  
LEFT CHANNEL  
RIGHT CHANNEL  
1
2
n
1
2
n
MSB  
LSB  
MSB  
LSB  
Figure 9 Split Rate Audio Mode Timing Diagram  
Notes:  
1. Figure 9 shows the timing for left justified however this is similar for right justified and I2S.  
2. The edges of LRCIN and LRCIN2 must be coincidental.  
March 2006, PD Rev 4.0  
13  
w
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