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WM8737CLGEFL 参数 Datasheet PDF下载

WM8737CLGEFL图片预览
型号: WM8737CLGEFL
PDF下载: 下载PDF文件 查看货源
内容描述: 用麦克风前置放大器的立体声ADC [Stereo ADC with Microphone Preamplifier]
分类和应用: 商用集成电路放大器
文件页数/大小: 40 页 / 413 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8737L  
Production Data  
DESCRIPTION  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
4
LRP  
0
Right, left & I2S modes – ADCLRC  
polarity  
1 = invert ADCLRC polarity  
0 = normal ADCLRC polarity  
DSP Mode – mode A/B select  
1 = MSB is available on 1st BCLK  
rising edge after ADCLRC rising edge  
(mode B)  
0 = MSB is available on 2nd BCLK  
rising edge after ADCLRC rising edge  
(mode A)  
6
7
MS  
0
0
Master / Slave Mode Control  
1: Master Mode  
0: Slave Mode  
SDODIS  
ADCDAT serial data pin disable  
0: ADCDAT pin enabled  
1: ADCDAT pin off (high impedance)  
Table 14 Audio Data Format Control  
Note: Right Justified mode does not support 32-bit data. If WL=11 in Right justified mode, the actual  
word length is 24 bits.  
To prevent any communication problems on the Audio Interface, the interface is disabled (ADCDAT  
tristated and floating) when the WM8737L starts up. Once the Audio Interface and sample rates have  
been programmed, the audio interface can be activated under software control by setting the AI bit  
(see “Power Management” section).  
MASTER CLOCK AND AUDIO SAMPLE RATES  
The master clock (MCLK) is used to operate the digital filters and the noise shaping circuits. The  
WM8737L supports a wide range of master clock frequencies, and can generate many commonly  
used audio sample rates directly from the master clock.  
There are two clocking modes:  
‘Normal’ mode supports master clocks of 128fs, 192fs, 256fs, 384fs, and their multiples  
USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in  
systems with a USB interface, and eliminates the need for an external PLL to generate  
another clock frequency for the audio ADC.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R8 (08h)  
6
0
CLKDIV2  
0
0
Master Clock Divide by 2  
1: MCLK is divided by 2  
0: MCLK is not divided  
Clocking Mode Select  
1: USB Mode  
Clocking and  
Sample Rate  
Control  
USB  
0: ‘Normal’ Mode  
5:1  
7
SR[4:0]  
0000  
0
Sample Rate Control  
Clock Ratio Autodetect  
(Slave Mode Only)  
0: Autodetect Off  
AUTO  
DETECT  
1: Autodetect On  
Table 15 Clocking and Sample Rate Control  
PD, Rev 4.4, January 2012  
28  
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