WM8737L
Production Data
NOISE GATE
When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise
pumping”, i.e. loud hissing noise during silence periods. The WM8737L has a noise gate function that
prevents noise pumping by comparing the signal level at the LINPUT1/2/3 and/or RINPUT1/2/3 pins
against a noise gate threshold, NGTH. The noise gate cuts in when:
Signal level at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic preamp gain [dB]
This is equivalent to:
Signal level at input pin [dB] < NGTH [dB]
When the noise gate is triggered, the PGA gain is held constant (preventing it from ramping up as it
would normally when the signal is quiet).
The table below summarises the noise gate control register. The NGTH control bits set the noise gate
threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps. Levels at
the extremes of the range may cause inappropriate operation, so care should be taken with set–up of
the function. Note that the noise gate only works in conjunction with the ALC function, and always
operates on the same channel(s) as the ALC (left, right, both, or none).
REGISTER
ADDRESS
BIT
LABEL
NGAT
DEFAULT
DESCRIPTION
R11 (0Bh)
0
Noise gate function enable
1 = enable
0
Noise Gate
Control
0 = disable
NGTH[2:0]
000
Noise gate threshold (with respect to
ADC output level)
4:2
000: -78dBFS
001: -72dBfs
… 6 dB steps
110: -42dBFS
111: -30dBFS
Table 13 Noise Gate Control
DIGITAL AUDIO INTERFACE
The digital audio interface uses three pins:
ADCDAT: ADC data output
ADCLRC: ADC data alignment clock
BCLK: Bit clock, for synchronisation
The digital audio interface takes the data from the internal ADC digital filters and places it on
ADCDAT and ADCLRC. ADCDAT is the formatted digital audio data stream output from the ADC
digital filters with left and right channels multiplexed together. ADCLRC is an alignment clock that
indicates whether Left or Right channel data is present on the ADCDAT line. ADCDAT and ADCLRC
are synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low
transition. ADCDAT is always an output. BCLK and ADCLRC may be inputs or outputs depending
whether the device is in master or slave mode (see Master and Slave Mode Operation, below).
Four different audio data formats are supported:
Left justified
Right justified
I2S
DSP mode
All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
PD, Rev 4.4, January 2012
24
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
