WM8737L
Production Data
CONTROL INTERFACE
SELECTION OF CONTROL MODE
The WM8737L is controlled by writing to registers through a serial control interface. A control word
consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is
accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each control
register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin
selects the interface format.
MODE
Low
INTERFACE FORMAT
2 wire
3 wire
High
Table 17 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
CSB latches in a complete control word consisting of the last 16 bits.
latch
CSB
SCLK
SDIN
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
control register address
control register data bits
Figure 17 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8737L supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device can be identified by one of two 7-bit address (this is not the same as
the 7-bit address of each register in the WM8737L).
The WM8737L interface can be written to only and cannot be read back. The controller indicates the
start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates
that a device address and data will follow. All devices on the 2-wire bus respond to the start condition
and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device
address received matches the address of the WM8737L and the R/W bit is ‘0’, indicating a write, then
the WM8737L responds by pulling SDIN low on the next clock pulse (ACK). If the address is not
recognised or the R/W bit is ‘1’, the WM8737L returns to the idle condition and wait for a new start
condition and valid address.
Once the WM8737L has acknowledged a correct address, the controller sends the first byte of control
data (B15 to B8, i.e. the WM8737L register address plus the first bit of register data). The WM8737L
then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then
sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the
WM8737L acknowledges again by pulling SDIN low.
The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
After receiving a complete address and data sequence the WM8737L returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at any point
during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
PD, Rev 4.4, January 2012
30
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
