Production Data
WM8737L
The clocking of the WM8737L is controlled using the CLKDIV2, USB, and SR control bits. Setting the
CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode.
Each combination of the SR4 to SR0 control bits selects one sample rate (see next page). The digital
filter characteristics are automatically adjusted to suit the MCLK and sample rate selected (see Digital
Filter Characteristics).
Since all sample rates are generated by dividing MCLK, their accuracy depends on the accuracy of
MCLK. If MCLK changes, the sample rates change proportionately. Note that some sample rates (e.g.
44.1kHz in USB mode) are approximated, i.e. they differ from their target value by a very small
amount. This is not audible, as the maximum deviation is only 0.27% (48.0214kHz instead of 48kHz
in USB mode - for comparison, a half-tone step corresponds to a 5.9% change in pitch).
In slave mode, it is possible to autodetect the audio clock rate ratio, instead of programming it. The
WM8737L can autodetect the following clock ratios:
CLKDIV2 = 0: MCLK = 128fs, 192fs, 256fs, or 384fs subject to MCLK < 40MHz
CLKDIV2 = 1: MCLK = 256fs, 384fs, 512fs, 768fs, 1024fs, 1536fs, subject to MCLK <
40MHz
MCLK
MCLK
CLKDIV2=1
ADC SAMPLE RATE
USB
SR [4:0]
FILTER
TYPE
CLKDIV2=0
Normal Clock Mode
12.288MHz
24.576MHz
16 kHz (MCLK/768)
24 kHz (MCLK/512)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
01010
11100
01100
00000
01110
11010
10000
11110
01011
11101
01101
00001
01111
11011
10001
11111
A
A
A
A
B
A
A
B
A
A
A
A
B
A
A
B
32 kHz (MCLK/384)
48 kHz (MCLK/256)
96 kHz (MCLK/128) (see Note 1)
22.05 kHz (MCLK/512)
44.1 kHz (MCLK/256)
11.2896MHz
18.432MHz
22.5792MHz
36.864MHz
88.2 kHz (MCLK/128) (see Note 1)
16 kHz (MCLK/1152)
24 kHz (MCLK/768)
32 kHz (MCLK/576)
48 kHz (MCLK/384)
96 kHz (MCLK/192) (see Note 1)
22.05 kHz (MCLK/768)
44.1 kHz (MCLK/384)
16.9344MHz
33.8688MHz
24.000MHz
88.2 kHz (MCLK/192) (see Note 1)
USB Mode
12.000MHz
16 kHz (MCLK/750)
22.0588 kHz (MCLK/544)
24 kHz (MCLK/500)
1
1
1
1
1
1
1
1
01010
11011
11100
01100
10001
00000
11111
01110
C
A
C
C
A
C
B
D
32 kHz (MCLK/375)
44.118 kHz (MCLK/272)
48 kHz (MCLK/250)
88.235 kHz (MCLK/136) (see Note 1)
96 kHz (MCLK/125)
Table 16 Master Clock and Sample Rates
Note 1: The 3D enhancement is not supported at sample frequencies of 88.2kHz, 88.235kHz,
and 96kHz. When using these sample frequencies the 3D enhancement function
should be bypassed by first setting register R13 (0Dh) to 1_110x_xxxx (1C0h), where
x_xxxx represents the required values for the ALC in the application, and then setting
register R28 (1Ch) to 0_0000_0100 (004h).
Note that the above sequence uses test bits that are not documented and the use of
these test bits, other than as described above, is not recommended and is not
supported.
PD, Rev 4.4, January 2012
29
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