WM8737L
Production Data
Standby mode 1 is achieved by powering down everything except the VMID source and gives a very
low power sleep mode. Wake-up may require a few milliseconds to ensure that the VREF voltage has
stabilized.
Standby mode 2 is achieved by not powering down VMID and VREF. The WM8737L can awaken
instantly from standby mode 2 because VREF is already stable.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R6 (06h)
8
VMID
0
VMID (necessary for all other functions)
VREF (necessary for all other functions)
Audio Interface
Power
Manageme
nt
7
VREF
AI
0
6
0
5
PGL
0
PGA Left
4
PGR
0
PGA Right
3
ADL
0
ADC Left
2
ADR
0
ADC Right
1:0
4
MICBIAS
LMBE
RMBE
00
0
see “Microphone Bias” section
Mic Boost Left (see “Input Signal Path”)
Mic Boost Right (see “Input Signal Path”)
R2 (02h)
R3 (03h)
4
0
Notes: All control bits are 0=OFF, 1=ON
Table 20 Power Management
REGISTER MAP
REGISTER ADDRESS REMARKS
(BIT 15 – 9)
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
R0 (00h)
R1 (01h)
R2 (02h)
R3 (03h)
R4 (04h)
R5 (05h)
0000000
0000001
Left PGA
LVU
RVU
LINVOL [7:0]
RINVOL [7:0]
Right PGA
0000010 Audio Path L
0000011 Audio Path R
0000100 3D Enhance
0000101 ADC Control
LINSEL
RINSEL
DIV2
MONOMIX
LMICBOOST
RMICBOOST
LMBE
LMZC
RMZC
LPZC
RPZC
LZCTO[1:0]
RZCTO[1:0]
3DE
RMBE
0
3DLC
3DUC
3DDEPTH
POLARITY
HPOR
0
LP
MONOUT
ADC
HPD
R6 (06h)
R7 (07h)
R8 (08h)
0000110 Power Mgmt VMID
VREF
SDODIS
AUTO
DETECT
0
AI
MS
CLK
DIV2
0
PGL
0
PGR
LRP
ADL
ADR
MICBIAS
FORMAT
USB
Mode
MBCTRL[1:0]
0000111 Audio Format
0001000 Clocking
0
0
WL
SR (Sample Rate Selection)
R9 (09h)
0001001 Mic Preamp
Control
0
0
0
0
0
0
RBYPEN LBYPEN
VMIDSEL [1:0]
R10 (0Ah)
0001010 Misc. biases
control
0
0
LINPUT1 RINPUT1
dc BIAS dc BIAS
ENABLE ENABLE
R11 (0Bh)
R12 (0Ch)
R13 (0Dh)
R14 (0Eh)
R15 (0Fh)
0001011
0001100
0001101
0001110
0001111
Noise Gate
ALC1
0
0
0
0
MAXGAIN
0
NGTH (Threshold)
0
NGAT
ALCSEL
Reserved (must write zeros)
ALCL (Target Level)
HLD (Hold Time)
ATK (Attack Time)
ALC2
ALCZCE
ALC3
0
DCY (Decay Time)
Reset
RESET (writing 000000000 to this register resets all registers to their default state)
Table 21 Control Register Map
PD, Rev 4.4, January 2012
32
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
