WM8737L
Production Data
1/fs
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC
BCLK
1 BCLK
1 BCLK
ADCDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 12 I2S Justified Audio Interface (assuming n-bit word length)
In DSP mode, the left channel MSB is available on either the 1st or 2nd rising edge of BCLK
(selectable by LRP) following a rising edge of ADCLRC. Right channel data immediately follows left
channel data. Depending on word length, BCLK frequency and sample rate, there may be unused
BCLK cycles between the LSB of the right channel data and the next sample.
Figure 13 DSP Mode A Mater Mode
Figure 14 DSP Mode B, Master Mode Audio Interface
PD, Rev 4.4, January 2012
26
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
