Production Data
WM8737L
REGISTER
ADDRESS
BIT
8:7
LABEL
DEFAULT
00
DESCRIPTION
ALC function select
R12 (0Ch)
ALCSEL[1:0]
ALC Control 1
00 = ALC off (PGA gain set by
register)
01 = Right channel only
10 = Left channel only
11 = Stereo (PGA registers unused)
Set maximum gain for the PGA
111 : +30dB
6:4
3:0
MAXGAIN
ALCL[3:0]
111
110 : +24dB
…..(-6dB steps)
001 : -6dB
000 : -12dB
1100
ALC target level – sets signal level
after PGA at ADC input in 1dB steps
0000: -18dB FS
0001: -17dB FS
…
1110: -4dB FS
1111: -3dB FS
R13 (0Dh)
3:0
HLD[3:0]
0000
ALC hold time before gain is increased
0000: 0ms
ALC Control 2
0001: 2.67ms
0010: 5.33ms
… (time doubles with every step)
1111: 43.691s
4
ALCZCE
ATK[3:0]
0
Enable zero-cross function for the ALC
gain updates
0: Zero-cross disabled
1: Zero-cross enabled
ALC attack (gain ramp-down) time
0000: 8.4ms
R14 (0Eh)
3:0
0010
ALC Control 3
0001: 16.8ms
0010: 33.6ms
… (time doubles with every step)
1010 or higher = 8.6s
ALC decay (gain ramp-up) time
0000: 33.6ms
7:4
DCY[3:0]
0011
0001: 67.2ms
0010: 134.4ms
… (time doubles with every step)
1010 or higher = 34.41s
Table 12 ALC Control
PEAK LIMITER
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a
limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dBFS), the PGA gain is
ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below
87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.
(Note: If ATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed
to prevent clipping when long attack times are used.)
PD, Rev 4.4, January 2012
23
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
