WM8352
Production Data
Figure 19 Control Interface Timing - 3-wire Control Mode (Write Cycle)
Figure 20 Control Interface Timing - 3-wire Control Mode (Read Cycle)
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA = +25oC, unless otherwise stated.
PARAMETER
SYMBOL
tCSU
tCHO
tSCY
tSCL
MIN
40
10
200
80
80
40
10
0
TYP
MAX
UNIT
ns
CSB falling edge to SCLK rising edge
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
ns
ns
SCLK pulse width low
ns
SCLK pulse width high
tSCH
tDSU
tDHO
tps
ns
SDATA to SCLK set-up time
SDATA to SCLK hold time
ns
ns
Pulse width of spikes that will be suppressed
SCLK falling edge to SDATA output transition
5
ns
tDL
40
ns
PD, February 2011, Rev 4.4
36
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
