WM8352
Production Data
10 SIGNAL TIMING REQUIREMENTS
10.1 SYSTEM CLOCK TIMING
tMCLKY
MCLK
tMCLKL tMCLKH
Figure 14 Master Clock Timing
Master Clock Timing
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
40
TYP
MAX
UNIT
MCLK cycle time
MCLK duty cycle
TMCLKY
ns
= high time / low time
60:40
40:60
10.2 AUDIO INTERFACE TIMING - MASTER MODE
Figure 15 Digital Audio Data Timing – Master Mode
Test Conditions
DCVDD = 1.8V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
tBCLKR
tBCLKF
tBCLKDS
tDL
MIN
TYP
MAX
3
UNIT
ns
BCLK rise time (10pF load)
BCLK fall time (10pF load)
3
ns
BCLK duty cycle
60:40
40:60
10
LRC propagation delay from BCLK falling edge
ADCDAT propagation delay from BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
ns
ns
ns
ns
tDDA
10
tDST
10
10
tDHT
PD, February 2011, Rev 4.4
32
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
