WM8352
Production Data
10.4 AUDIO INTERFACE TIMING - TDM MODE
In TDM mode, it is important that two ADC devices to not attempt to drive the ADCDAT pin
simultaneously. The timing of the WM8352 ADCDAT tri-stating at the start and end of the data
transmission is described in Figure 17 and the table below.
Figure 17 Digital Audio Data Timing - TDM Mode
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA=+25oC, Master Mode, fs=48kHz, 24-bit data, unless otherwise stated.
PARAMETER
Audio Data Timing Information
CONDITIONS
MIN
TYP
MAX
UNIT
ADCDAT setup time from BCLK falling edge
DCVDD =
3.6V
5
15
5
ns
ns
ns
ns
DCVDD =
1.8V
ADCDAT release time from BCLK falling edge
DCVDD =
3.6V
DCVDD =
1.8V
15
PD, February 2011, Rev 4.4
34
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
