Production Data
WM8352
10.5 CONTROL INTERFACE TIMING
Figure 18 Control Interface Timing - 2-wire Control Mode
Test Conditions
DCVDD = 1.8V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, unless otherwise stated.
PARAMETER
SYMBOL
MIN
0
TYP
MAX
UNIT
kHz
us
SCLK Frequency
526
SCLK Low Pulse-Width
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
t1
t2
t3
t4
t5
t6
t7
t8
t9
tps
1.3
600
600
600
100
ns
ns
ns
ns
SDATA, SCLK Rise Time
SDATA, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
300
300
ns
ns
600
0
ns
900
5
ns
Pulse width of spikes that will be suppressed
ns
PD, February 2011, Rev 4.4
35
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