Production Data
WM8352
10.3 AUDIO INTERFACE TIMING - SLAVE MODE
Figure 16 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD = 1.8V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
tBCY
MIN
50
20
20
10
10
10
10
TYP
MAX
UNIT
ns
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
tBCH
tBCL
tLRSU
tLRH
ns
ns
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
DACDAT set-up time to BCLK rising edge
ADCDAT propagation delay from BCLK falling edge
ns
ns
tDH
ns
tDS
ns
tDD
10
ns
PD, February 2011, Rev 4.4
33
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