WM8216
Production Data
SERIAL INTERFACE: REGISTER READ-BACK
Figure 16 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus
as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing
address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of
corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge
of SCK). Note that pin SDO is shared with an output pin, OP[9], therefore OEB should always be
held low and the OPD register bit should be set low when register read-back data is expected on this
pin. The next word may be read in to SDI while the previous word is still being output on SDO.
Figure 16 Serial Interface Register Read-back
NORMAL OPERATING MODES
Table 3 below shows the normal operating modes of the device. The MCLK speed can be specified
along with the MCLK:VSMP ratio to achieve the desired sample rate.
NUMBER
OF
CHANNELS
DESCRIPTION
CDS
AVAILABLE
MAXIMUM
SAMPLE
RATE
TIMING REQUIREMENTS
CHANNEL
MODE
SETTINGS
2
1
Two channel
Pixel-by-Pixel
YES
YES
30 MSPS
MCLK max = 60Mhz
MONO = 0
Minimum MCLK:VSMP ratio = 2:1
MCLK max = 45Mhz
TWOCHAN = 1
MONO = 1
One channel
Pixel-by-Pixel
45 MSPS
Minimum MCLK:VSMP ratio = 1:1
TWOCHAN = 0
Table 3 WM8216 Normal Operating Modes
Note: In one channel mode the WM8216 can operate at 60MHz but DNL/INL values cannot
be guaranteed.
Table 4 below shows the different channel mode register settings required to operate the 8216 in 1
and 2 channel modes.
MONO
TWOCHAN
CHAN
MODE DESCRIPTION
0
1
X
0
2-channel
1
1
1
0
0
1
1-channel mode. Odd Channel
1-channel mode. Even Channel
Invalid mode
1
X
Table 4 Sampling Mode Summary
Note: Unused input pins should be connected to AGND.
PD Rev 4.0 March 2007
20
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
