欢迎访问ic37.com |
会员登录 免费注册
发布采购

WM8216SEFL/R 参数 Datasheet PDF下载

WM8216SEFL/R图片预览
型号: WM8216SEFL/R
PDF下载: 下载PDF文件 查看货源
内容描述: 60MSPS 10位2通道CCD数字转换器 [60MSPS 10-bit 2-channel CCD Digitiser]
分类和应用: 转换器
文件页数/大小: 27 页 / 460 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
 浏览型号WM8216SEFL/R的Datasheet PDF文件第19页浏览型号WM8216SEFL/R的Datasheet PDF文件第20页浏览型号WM8216SEFL/R的Datasheet PDF文件第21页浏览型号WM8216SEFL/R的Datasheet PDF文件第22页浏览型号WM8216SEFL/R的Datasheet PDF文件第24页浏览型号WM8216SEFL/R的Datasheet PDF文件第25页浏览型号WM8216SEFL/R的Datasheet PDF文件第26页浏览型号WM8216SEFL/R的Datasheet PDF文件第27页  
WM8216  
Production Data  
REGISTER  
BIT  
NO  
BIT  
NAME(S)  
DEFAULT  
DESCRIPTION  
Setup  
Register 3  
3:0  
RLCDAC[3:0]  
1111  
Controls RLCDAC driving VRLC/VBIAS pin to define single ended signal  
reference voltage or Reset Level Clamp voltage. See Electrical Characteristics  
section for ranges.  
5:4  
CDSREF[1:0]  
01  
CDS mode reset timing adjust.  
00 = Advance reset sample by 1 MCLK period (relative to default).  
01 = Default reset sample position.  
10 = Delay reset sample by 1 MCLK period (relative to default)  
11 = Delay reset sample by 2 MCLK periods (relative to default)  
When MONO=0 this register bit has no effect  
Monochrome mode channel select.  
6
7
CHAN  
0
0
00 = Odd channel select  
01 = Even channel select  
Must be set to 0  
Not Used  
Software  
Reset  
Any write to Software Reset causes all register bits to be reset. It is  
recommended that a software reset be performed after a power-up before any  
other register writes.  
Setup  
Register 5  
0
1
3
ODDPD  
EVENPD  
ADCPD  
0
0
0
When set powers down odd S/H, PGA  
When set powers down even S/H, PGA  
When set powers down ADC. Allows reduced power consumption without  
powering down the references which have a long time constant when  
switching on/off due to the external decoupling capacitors.  
When set powers down 4-bit RLCDAC, setting the output to a high impedance  
state and allowing an external reference to be driven in on the VRLC/VBIAS  
pin.  
4
VRLCDACPD  
0
5
6
ADCREFPD  
VRXPD  
0
0
0
When set disables VRT, VRB buffers to allow external references to be used.  
When set disables VRX buffer to allow an external reference to be used.  
Must be set to 0  
7
Not Used  
Setup  
Register 6  
4:0  
5
Not Used  
RLCEN  
00000  
1
Must be set to 0  
Reset Level Clamp Enable. When set Reset Level Clamping is enabled. The  
method of clamping is determined by CLAMPCTRL.  
6
7
CLAMPCTRL  
0
0 = RLC switch is controlled directly from RSMP input pin:  
RSMP = 0: switch is open  
RMSP = 1: switch is closed  
1 = RLC switch is controlled by logical combination of RSMP and VSMP.  
RSMP && VSMP = 0: switch is open  
RSMP && VSMP = 1: switch is closed  
Must be set to 0  
Not Used  
0
PD Rev 4.0 March 2007  
23  
w
 复制成功!