WM8199
Production Data
CONTROL INTERFACE
The internal control registers are programmable via the serial digital control interface. The register
contents can be read back via the serial interface on pin OP[7]/SDO.
It is recommended that a software reset is carried out after the power-up sequence, before writing to
any other register. This ensures that all registers are set to their default values (as shown in Table
5).
SERIAL INTERFACE: REGISTER WRITE
Figure 16 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit
address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data
word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK.
When the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the
appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode.
SCK
a5
0
a3
a2
a1
a0
b7
b6
b5
b4
b3
b2
b1
b0
SDI
Address
Data Word
SEN
Figure 16 Serial Interface Register Write
A software reset is carried out by writing to Address “000100” with any value of data, (i.e. Data Word
= XXXXXXXX).
SERIAL INTERFACE: REGISTER READ-BACK
Figure 17 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus
as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing
address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of
corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge
of SCK). Note that pin SDO is shared with an output pin, OP[7], therefore OEB should always be
held low when register read-back data is expected on this pin. The next word may be read in to SDI
while the previous word is still being output on SDO.
SCK
a5
1
a3 a2 a1 a0
x
x
x
x
x
x
x
x
SDI
Address
Data Word
SEN
SDO/
OP[7]
d7 d6 d5 d4 d3 d2 d1 d0
Output Data Word
OEB
Figure 17 Serial Interface Register Read-back
TIMING REQUIREMENTS
To use this device a master clock (MCLK) of up to 40MHz and a per-pixel synchronisation clock
(VSMP) of up to 20MHz are required. These clocks drive a timing control block, which produces
internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum
sample rates for the various modes are shown in Table 4.
PD Rev 3.2 November 2003
17
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
