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WM8199SCDS 参数 Datasheet PDF下载

WM8199SCDS图片预览
型号: WM8199SCDS
PDF下载: 下载PDF文件 查看货源
内容描述: 20MSPS的16位CCD数字转换器 [20MSPS 16-bit CCD Digitiser]
分类和应用: 转换器
文件页数/大小: 30 页 / 360 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8199  
Production Data  
MCLK  
VSMP  
VS  
RS/CL (CDSREF = 00)  
RS/CL (CDSREF = 01)  
RS/CL (CDSREF = 10)  
RS/CL (CDSREF = 11)  
Figure 10 Reset Sample and Clamp Timing  
For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed  
with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described  
above. The VRLC/VBIAS pin is sampled by Rs at the same time as Vs samples the video level in this  
mode.  
OFFSET ADJUST AND PROGRAMMABLE GAIN  
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset  
DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset for each  
channel are independently programmable by writing to control bits DAC[7:0] and PGA[7:0].  
The gain characteristic of the WM8199 PGA is shown in Figure 11. Figure 12 shows the maximum  
device input voltage that can be gained up to match the ADC full-scale input range (3V).  
8
7
6
5
4
3
2
1
0
4.5  
4
3.5  
3
2.5  
2
1.5  
1
0.5  
0
0
64  
128  
192  
256  
0
64  
128  
192  
256  
Gain register value (PGA[7:0])  
Gain register value (PGA[7:0])  
Figure 11 PGA Gain Characteristic  
Figure 12 Peak Input Voltage to Match ADC Full-scale Range  
In colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order  
(Red Green Blue Red…) by pulsing the ACYC/RLC pin, or controlled via the FME,  
ACYCNRLC and INTM[1:0] bits. Refer to the Line-by-Line Operation section for more details.  
ADC INPUT BLACK LEVEL ADJUST  
The output from the PGA should be offset to match the full-scale range of the ADC (3V). For  
negative-going input video signals, a black level (zero differential) output from the PGA should be  
offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input  
signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11.  
Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential  
input voltage gives mid-range ADC output).  
PD Rev 3.2 November 2003  
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