WM8199
Production Data
POWER MANAGEMENT
Power management for the device is performed via the Control Interface. The device can be powered
on or off completely by setting the EN bit and SELPD bit low. Alternatively, when control bit SELPD is
high, only blocks selected by further control bits (SELDIS[3:0]) are powered down. This allows the
user to optimise power dissipation in certain modes, or to define an intermediate standby mode to
allow a quicker recovery into a fully active state. In Line-by-line operation, the green and blue channel
PGAs are automatically powered down.
All the internal registers maintain their previously programmed value in power down modes and the
Control Interface inputs remain active. Table 2 summarises the power down control bit functions.
EN
0
SELDPD
0
0
1
Device completely powers down.
1
Device completely powers up.
X
Blocks with respective SELDIS[3:0] bit high are disabled.
Table 2 Power Down Control
LINE-BY-LINE OPERATION
Certain linear sensors (e.g. Contact Image Sensors) give colour output on a line-by-line basis. i.e. a
full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order to
accommodate this type of signal the WM8199 can be set into Monochrome mode, with the input
channel switched by writing to control bits CHAN[1:0] between every line. Alternatively, the WM8199
can be placed into colour line-by-line mode by setting the LINEBYLINE control bit. When this bit is
set the green and blue processing channels are powered down and the device is forced internally to
only operate in MONO mode (because only one colour is sampled at a time) through the red channel.
Figure 19 shows the signal path when operating in colour line-by-line mode.
VRLC/VBIAS
VSMP
MCLK
CL
RS VS TIMING CONTROL
R
8
OFFSET
MUX
OFFSET
DAC
G
B
16-
BIT
ADC
DATA
I/O
PORT
RINP
RLC
RLC
RLC
CDS
+
PGA
8
+
OP[7:0]
INPUT
MUX
R
I/P SIGNAL
POLARITY
ADJUST
PGA
MUX
G
GINP
BINP
B
SEN/STB
SCK/RNW
SDI/DNA
RLC/ACYC
NRESET
CONFIGURABLE
SERIAL/
PARALLEL
CONTROL
INTERFACE
RLC
DAC
4
Figure 19 Signal Path When in Line-by-Line Mode
In this mode the input multiplexer and (optionally) the PGA/Offset register multiplexers can be auto-
cycled by the application of pulses to the RLC/ACYC input pin by setting the ACYCNRLC register bit.
See figure 4 for detailed timing. The multiplexers change on the first MCLK rising edge after
RLC/ACYC is taken high. A write to the auto-cycle reset register causes these multiplexers to be
reset; selecting the RINP pin and the RED offset/gain registers. Alternatively, all three multiplexers
can be controlled via the serial interface by writing to register bits INTM[1:0] to select the desired
colour. It is also possible for the input multiplexer to be controlled separately from the PGA and
Offset multiplexers. Table 3 describes all the multiplexer selection modes that are possible.
FME ACYCNRLC
NAME
Internal,
no force mux
DESCRIPTION
0
0
1
0
1
0
Input mux, offset and gain registers determined by
internal register bits INTM1, INTM0.
Auto-cycling,
no force mux
Input mux, offset and gain registers auto-cycled, RINP
→ GINP → BINP → RINP… on RLC/ACYC pulse.
Internal,
Input mux selected from internal register bits FM1, FM0;
force mux
Offset and gain registers selected from internal register
bits INTM1, INTM0.
1
1
Auto-cycling,
force mux
Input mux selected from internal register bits FM1, FM0;
Offset and gain registers auto-cycled, RED → GREEN
→ BLUE → RED… on RLC/ACYC pulse.
Table 3 Colour Selection Description in Line-by-Line Mode
PD Rev 3.2 November 2003
19
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
