WM8199
Production Data
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain,
V3
=
V2 208/(283- PGA[7:0]) .............................................. Eqn. 5
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 16-bit unsigned number, with input range configured by
PGAFS[1:0].
D1[15:0] = INT{ (V3 /VFS
D1[15:0] = INT{ (V3 /VFS
D1[15:0] = INT{ (V3 /VFS
)
)
)
65535} + 32767 PGAFS[1:0] = 00 or 01 ...... Eqn. 6
65535} PGAFS[1:0] = 11 ............... Eqn. 7
65535} + 65535 PGAFS[1:0] = 10 ............... Eqn. 8
where the ADC full-scale range, VFS = 3V
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP.
D2[15:0] = D1[15:0]
(INVOP = 0) ...................... Eqn. 9
(INVOP = 1) ...................... Eqn. 10
D2[15:0] = 65535 – D1[15:0]
OUTPUT FORMATS
The digital data output from the ADC is available to the user in 8 or 4-bit wide multiplexed formats by
setting control bit MUXOP[1:0]. Latency of valid output data with respect to VSMP is programmable
by writing to control bits DEL[1:0]. The latency for each mode is shown in the Operating Mode Timing
Diagrams section.
Figure 14 shows the output data formats for Modes 1 – 2 and 4 – 6. Figure 15 shows the output data
formats for Mode 3. Table 1 summarises the output data obtained for each format.
MCLK
MCLK
8+8-BIT
OUTPUT
8+8-BIT
OUTPUT
A
B
A
B
4+4+4+4-BIT
OUTPUT
4+4+4+4-BIT
OUTPUT
A
B
C
D
A B A B C
D
Figure 14 Output Data Formats
Figure 15 Output Data Formats
(Mode 3)
(Modes 1 − 2, 4 − 6)
OUTPUT
FORMAT
MUXOP[1:0]
00, 01, 10
11
OUTPUT
PINS
OUTPUT
8+8-bit
multiplexed
OP[7:0]
A = d15, d14, d13, d12, d11, d10, d9, d8
B = d7, d6, d5, d4, d3, d2, d1,d0
4+4+4+4-bit
(nibble)
OP[7:4]
A = d15, d14, d13, d12
B = d11, d10, d9, d8
C = d7, d6, d5, d4
D = d3, d2, d1, d0
Table 1 Details of Output Data Shown in Figure 14 and Figure 15.
PD Rev 3.2 November 2003
16
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
