W90N745CD/W90N745CDG
PLL Control Register 1（PLLCON1）
W90N745 provides extra PLL to provide 12.288/16.934 MHz clock source to Audio Controller. It uses the
same 15MHz crystal clock input source with system PLL mentioned above.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
PLLCON1
PLL Control Register 1
0xFFF0_0010
R/W
0x0001_0000
31
23
15
30
22
14
29
21
13
5
28
RESERVED
20
27
26
25
17
9
24
19
11
3
18
10
16
PWDEN1
8
RESERVED
12
FBDV1
7
6
4
2
1
0
FBDV1
OTDV1
INDV1
BITS
DESCRIPTION
[31:17]
RESERVED
PWDEN1
-
PLL1 power down enable
0 = PLL1 is in normal mode
1 = PLL1 is in power down mode (default)
[16]
PLL1 VCO output clock feedback divider
Feedback Divider divides the output clock from VCO of PLL1.
[15:7]
FBDV1
OTDV1
INDV1
PLL1 output clock divider
OTDV1 [6:5]
Divided by
0
0
1
1
0
1
0
1
1
2
2
4
[6:5]
[4:0]
PLL1 input clock divider
Input divider divides the input reference clock into the PLL1.
Publication Release Date: September 22, 2006
- 49 -
Revision A2
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