W90N745CD/W90N745CDG
Table 6.2.13 and Table 6.2.14
Using little-endian and byte access, Program/Data path between register and external memory.
BA = Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
BAL = Address whose LSB is 0,2,4,6,8,A,C,E BAU = Address whose LSB is 1,3,5,7,9,B,D,F
Table 6.2.13 Byte access write operation with little Endian
ACCESS OPERATION
XD Width
WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)
Half Word Byte
31 31
Bit Number
0
0
ABCD
ABCD
CPU Reg Data
SA
BAL
BAU
31
BA
Bit Number
SD
31
0
0
31
0
D D D D
D D D D
D D D D
Bit Number
ED
7 0
D
15 8
D
7 0
D
XA
BAL
UA
BAL
AU
BA
XA
nWBE [1-0] /
SDQM [1-0]
Bit Number
XD
15 0
X D
15 0
D X
7 0
D
Bit Number
Ext. Mem Data
Timing Sequence
7 0
D
15 8
D
7 0
D
Table 6.2.14 Byte access read operation with Little Endian
ACCESS OPERATION
READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)
XD Width
Half Word
Byte
Bit Number
CPU Reg Data
7 0
D
7 0
C
7 0
D
SA
BAL
BAU
BA
Bit Number
SD
7 0
D
7 0
C
7 0
D
Bit Number
ED
7 0
D
7 0
C
7 0
D
XA
BAL
UA
BAL
AU
BA
XA
SDQM [1-0]
Bit Number
XD
15 0
CD
15 0
CD
7 0
D
Bit Number
Ext. Mem Data
15 0
CD
7 0
D
Timing Sequence
- 36 -
WINBOND [ WINBOND ]
