W90N745CD/W90N745CDG
Table 6.2.11 and Table 6.2.12
Using little-endian and half-word access, Program/Data path between register and external memory.
HA = Address whose LSB is 0,2,4,6,8,A,C,E X = Don’t care
nWBE [1-0] / SDQM [1-0] = A means active and U means inactive
Table 6.2.11 Half-word access write operation with little Endian
ACCESS OPERATION
XD Width
WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)
Half Word Byte
31 31
Bit Number
0
0
ABCD
ABCD
CPU Reg Data
SA
HA
HA
Bit Number
SD
Bit Number
ED
31
CD CD
31
0
31
CD CD
0
31
CD CD
0
0
7 0
D
7 0
C
CD CD
XA
HA
HA
XA
HA+1
XA
nWBE [1-0] /
SDQM [1-0]
AA
Bit Number
XD
15 0
CD
7 0
D
7 0
C
Bit Number
Ext. Mem Data
15 0
CD
7 0
D
7 0
C
Timing Sequence
1st write
2nd write
Table 6.2.12 Half-word access read operation with Little Endian
ACCESS OPERATION
XD Width
READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)
Half Word
Byte
Bit Number
CPU Reg Data
15 0
CD
15 0
CD
SA
HA
HA
Bit Number
SD
15 0
CD
15 0
CD
Bit Number
ED
15 0
CD
15 0
XD
15 0
CD
XA
HA
AA
HA
XA
HA+1
XA
SDQM [1-0]
Bit Number
XD
15 0
CD
7 0
D
7 0
C
Bit Number
Ext. Mem Data
15 0
CD
7 0
D
7 0
C
Timing Sequence
1st read
2nd read
Publication Release Date: September 22, 2006
Revision A2
- 35 -
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