W90N745CD/W90N745CDG
Table 6.2.7 Byte access write operation with Big Endian
ACCESS OPERATION
XD WIDTH
WRITE OPERATION (CPU REGISTER EXTERNAL MEMORY)
HALF WORD BYTE
31 31
Bit Number
0
0
ABCD
ABCD
CPU Reg Data
SA
BAL
BAU
31
BA
Bit Number
SD
31
0
0
31
0
D D D D
D D D D
D D D D
Bit Number
ED
15 8
D
7 0
D
7 0
D
XA
BAL
AU
BAL
UA
BA
XA
nWBE [1-0] /
SDQM [1-0]
Bit Number
XD
15 0
D X
15 0
X D
7 0
D
Bit Number
Ext. Mem Data
Timing Sequence
15 8
D
7 0
D
7 0
D
Table 6.2.8 Byte access read operation with Big Endian
ACCESS OPERATION
XD WIDTH
READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)
HALF WORD
BYTE
Bit Number
CPU Reg Data
7 0
C
7 0
D
7 0
D
SA
BAL
BAU
BA
Bit Number
SD
7 0
C
7 0
D
7 0
D
Bit Number
ED
7 0
C
15 8
D
7 0
D
XA
BAL
AU
BAL
UA
BA
XA
SDQM [1-0]
Bit Number
XD
15 0
CD
15 0
CD
7 0
D
Bit Number
Ext. Mem Data
Timing Sequence
15 0
CD
7 0
D
Publication Release Date: September 22, 2006
Revision A2
- 33 -
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