W90N745CD/W90N745CDG
Table 6.2.6 Half-word access read operation with Big Endian
ACCESS OPERATION
XD WIDTH
READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)
HALF WORD
BYTE
Bit Number
CPU Reg Data
15 0
CD
15 0
DC
SA
HA
HA
Bit Number
SD
15 0
CD
15 0
DC
Bit Number
ED
15 0
CD
15 0
DX
15 0
DC
XA
HA
AA
HA
XA
HA+1
XA
SDQM [1-0]
Bit Number
XD
15 0
CD
7 0
D
7 0
C
Bit Number
Ext. Mem Data
15 0
CD
7 0
D
7 0
C
Timing Sequence
1st read
2nd read
Table 6.2.7 and Table 6.2.8
Using big-endian and byte access, Program/Data path between register and external memory.
BA = Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
BAL = Address whose LSB is 0,2,4,6,8,A,C,E BAU = Address whose LSB is 1,3,5,7,9,B,D,F
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