W90N745CD/W90N745CDG
Table 6.2.4 Word access read operation with Big Endian
ACCESS OPERATION
XD WIDTH
READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)
HALF WORD BYTE
31 31
Bit Number
0
0
CDAB
DCBA
CPU Reg Data
SA
WA
WA
Bit Number
SD
Bit Number
ED
31
CD AB
31
0
31
D C B A
31
0
31
0
0
31
D X X X
0
31
0
0
31
0
CD XX
CD AB
D C X X
D C B X
D C B A
XA
WA
WA+2
WA
WA+1
WA+2
WA+3
SDQM [1-0]
AA
AA
XA
XA
XA
XA
Bit Number
XD
15 0
CD
15 0
AB
7 0
D
7 0
C
7 0
B
7 0
A
Bit Number
Ext. Mem Data
15 0
CD
15 0
AB
2nd read
7 0
D
7 0
C
7 0
B
7 0
A
Timing Sequence
1st read
1st read
2nd read
3rd read
4th read
Table 6.2.5 and Table 6.2.6
Using big-endian and half-word access, Program/Data path between register and external memory.
HA = Address whose LSB is 0,2,4,6,8,A,C,E X = Don’t care
nWBE [1-0] / SDQM [1-0] = A means active and U means inactive
Table 6.2.5 Half-word access write operation with Big Endian
ACCESS OPERATION
XD WIDTH
WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)
HALF WORD BYTE
31 31
Bit Number
0
0
ABCD
ABCD
CPU Reg Data
SA
HA
HA
Bit Number
SD
Bit Number
ED
31
CD CD
31
0
31
CD CD
0
31
CD CD
0
0
7 0
C
7 0
D
CD CD
XA
HA
HA
XA
HA+1
XA
nWBE [1-0] /
SDQM [1-0]
AA
Bit Number
XD
15 0
CD
7 0
C
7 0
D
Bit Number
Ext. Mem Data
15 0
CD
7 0
C
7 0
D
Timing Sequence
1st write
2nd write
Publication Release Date: September 22, 2006
Revision A2
- 31 -
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