W90N745CD/W90N745CDG
31
23
15
30
22
14
29
21
28
20
12
4
27
Reserved
19
Reserved
26
18
10
25
17
9
24
16
8
13
Reserved
5
11
WTCLK nDBGACK_EN WTTME
7
6
3
2
1
0
WTE
WTIE
WTIS
WTIF
WTRF
WTRE
WTR
BITS
DESCRIPTIONS
[31:11]
Reserved
WTCLK
Reserved
Watchdog Timer Clock
This bit is used for deciding whether the Watchdog timer clock input is
divided by 256 or not. Clock source of Watchdog timer is Crystal
input.
[10]
0 = Using original clock input
1 = The clock input will be divided by 256
NOTE: When WTTME = 1, set this bit has no effect on WDT clock
(using original clock input).
ICE debug mode acknowledge enable
0 = When DBGACK is high, the Watchdog timer counter will be
held
[9]
nDBGACK_EN
1 = No matter DBGACK is high or not, the Watchdog timer counter
will not be held
Watchdog Timer Test Mode Enable
For reasons of efficiency, the 26-bit counter within the Watchdog
timer is considered as two independent 13-bit counters in the test
mode. They are operated concurrently and separately during the test.
This approach can save a lot of time spent in the test. When the 13-
bit counter overflows, a Watchdog timer interrupt is generated.
[8]
[7]
WTTME
0 = Put the Watchdog timer in normal operating mode
1 = Put the Watchdog timer in test mode
Watchdog Timer Enable
0 = Disable the Watchdog timer (This action will reset the internal
counter)
WTE
1 = Enable the Watchdog timer
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WINBOND [ WINBOND ]
